1. Technical Field of the Invention
The present invention relates to a non-volatile memory cell comprising dielectric layers at low dielectric constant.
Although not limited thereto, the invention relates, in particular, but not exclusively, to a non-volatile memory cell of the Flash type, comprising dielectric layers at low dielectric constant and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of Related Art
As it is well known, the Flash EEPROM memory electronic devices integrated on semiconductor comprise a plurality of matrix organized non-volatile memory cells 1; i.e., the cells are organized in rows, called word lines WL, and columns, called bit lines BL as shown in FIG. 1a. 
Each non-volatile cell 1 comprises a floating gate MOS transistor as shown in FIG. 1b. The floating gate region FG of the floating gate transistor is realized above the channel region CH realized in the semiconductor substrate 2 and it is separated from the latter by means of a thin tunnel oxide layer 3, whose thickness is between 6 and 12 nm. A control gate region CG is capacitively coupled to the floating gate region FG by means of a single dielectric layer 7 (e.g., an oxide) or by means of the superposition of several dielectric layers for example of the ONO (oxide/nitride/oxide) type.
FIGS. 1b and 1c also show an enlarged view of the sections on a vertical plane of a cell along the channel length L and width W.
The other regions of the transistor are the usual drain D, source S, and body terminals. Metallic electrodes are provided for contacting drain and source terminal with control gate region CG terminals in order to be able to apply pre-established voltage values to the memory cell 1.
The charge stored in the floating gate region FG determines the logic state of the cell 1 by modifying its voltage threshold: fundamental characteristic of the memory cell 1 is in fact that of having two states, one with low threshold voltage (“erased” cell) and one with high threshold voltage (“written” cell). The voltage is applied from outside the control gate region CG, but the electrode effectively controlling the channel state is the floating gate region FG.
The floating gate region FG voltage does not depend only on the control gate region CG voltage, but also on the source, drain and bulk potentials, according to this relation:
                    V        FG            =                                    Q            FG                                C            TOT                          +                              ∑                                          i                =                S                            ,              B              ,              D              ,              G                                ⁢                                    α              i                        ·                          V              i                                            ⁢                            Where      ⁢              :              ⁢                            α      i        =                                        C            i                    /                      C            TOT                          <                  1          ⁢                                          ⁢                      C            TOT                              =                        ∑                                    i              =              S                        ,            B            ,            D            ,            G                          ⁢                  C          i                    In the calculation of the capacitive relations the capacitors get close to capacitors having plane and parallel plates, so:
                    α        G            =                                    C            G                                C            TOT                          =                  1                      (                          1              +                                                W                                      W                    +                    A                                                  ·                                                      t                    ONO                                                        t                    ox                                                                        )                                ⁢                            α              S        ,        B        ,        D              =                            C                      S            ,            B            ,            D                                    C          TOT                    =                                    L                          S              ,              B              ,              D                                L                          (                      1            +                                                            W                  +                  A                                W                            ·                                                t                  ox                                                  t                  ONO                                                              )                    
where: Qfg=total charge stored in the FG; Ctot=total capacitance related to the FG, equal to the sum of the partial capacitances related to the i-th element; αi=capacitive coupling coefficient of the FG with the i-th element; Vi=voltage of the i-th element; A=total length of the superposition of FG and insulating oxide (FOX); tONO=thickness of the interpoly dielectric (7) tox=thickness of the tunnel oxide (3) Li=efficient electric length of the superposition region of FG and i-th element, where i can assume the S=source, B=body, D=drain, G=gate and W=channel width values
From these relations the importance of the form and of the profile of the floating gate region FG is understood. In particular, it becomes necessary that such region is extended on the field oxide FOX formed in the semiconductor substrate 2 in order to protrude therefrom forming gills indicated with “A” in FIG. 1c. The function of the gills A is that of making the capacitance between the two poly (Cg) predominant with respect to the others and of having the channel controlled by the control gate region CG. The size of the gill A further influences the gate capacitive coupling value (αg): a reduction of this parameter has a strong impact on the performance of the cell in terms of programming and erasing time.
The extension of the gill A is thus a critical parameter of the cell geometry. Another critical parameter is also that of the spacing size between two consecutive floating gate regions FG indicated with “H” in FIG. 1c. 
A known method flow for realizing these Flash memory cells 1 integrated on a semiconductor substrate 2 is schematically shown in FIGS. 2–5. In these figures vertical section views are shown in a direction parallel to the “Word Lines”.
This known method provides the formation in the substrate of a plurality of active areas wherein the memory cells will be realized being separated one another by portions of a field oxide layer FOX. On the substrate 2 a first dielectric layer 3 called “Tunnel Oxide” and a polycrystalline silicon layer 4 called POLY1 are then formed.
This polycrystalline silicon layer 4, whose thickness is of around 50–150 nm, is for example formed by means of LPCVD (Low Pressure Chemical Vapor Deposition). This polycrystalline silicon layer 4 is possibly doped in order to reduce its resistivity, e.g., with an implant of either phosphoric or arsenic or in situ by adding a suitable material, e.g., phosphine, to the deposition environment.
The method goes on with the definition of the layer 4 to realize a plurality of polycrystalline silicon stripes 5 parallel one another. These stripes 5 are separated and insulated from the substrate 2 by means of the oxide layer 3 as shown in FIG. 4.
In particular, in this step a layer 6 of photosensitive material called resist is deposited on the surface of the polycrystalline silicon layer 4 and it is exposed with a suitable radiation in predetermined areas non-protected by a mask. The portions of resist selectively exposed to the radiation have a removing speed higher than that of the non-exposed areas and so they can be removed by means of a chemical solution called developer (FIG. 3). After lithographic definition a dry etching of the polycrystalline silicon stripes 5 is performed to define the floating gate regions FG (FIG. 5).
After depositing an interpoly dielectric layer 7, the standard method flow continues with the definition of the “Word Lines” by forming a polycrystalline silicon layer 8 (called POLY2).
The “Word Lines” are then defined through a photolithographic method which provides the use of a resist mask so that these word lines are arranged perpendicularly with respect to the polysilicon stripes 5.
Although advantageous under many aspects, this method flow has several drawbacks. In fact, the lithographic transfer of the mask pattern is highly critical and it limits the reduction of the spacing between two consecutive polycrystalline silicon stripes 5.
A difficulty is that of solving structures of lower sizes with respect to the wave length used in the exposition (generally 248 nm or 193 nm). Moreover, the light transmitted through the photoresist layer is reflected from the substrate generating interference phenomena, which cause a degeneration of the pattern transferred from the mask. Normally, in order to reduce the amount of reflected radiation an anti-reflecting material (BARC) is used, which is deposited in the form of layer below the resist layer 6 and which is removed during the etching of the polycrystalline silicon stripes 5.
The interference phenomena causing the degeneration of the pattern transferred from the mask can be reduced also by depositing an oxide layer above the pblycrystalline silicon layer 4, which is then removed by means of a dry etching or a final etching solution (so-called “hard mask” method).
Different methods have been developed in the prior art with the aim of improving the pattern definition and thus reducing the spacing between consecutive floating gate regions.
A known method provides the use of a so-called “phase shift” (PSM) mask. This mask id provided with an added layer called phase-shifter, placed on the edges of the drawn structures, which allows to invert the phase of the light crossing it while, at the same time, it destructively interferes with the light crossing the uncovered areas. In this way the splitting of the thin stripes is increased. Even if this method allows to improve the lithographic definition of the floating gate region, it is quite complex and expensive to be implemented. Moreover, this method does not allow to realize openings in the polycrystalline silicon layer smaller than 140 nm +/−10 nm with the lithography 248 nm and smaller than 115 nm +/−10 nm with the lithography 193 nm, and it suffers from the lack of a suitable level of control and intra-die and intra-wafer repeatability.
Another known method is the definition of structures having controlled size, such as for example spacers similar to those used in the definition of the transistors of the LDD type in a sacrificial material (or more suitably in a combination of sacrificial materials) deposited above the polycrystalline silicon layer (POLY1) to be defined to form the floating gate region. By aligning the etching with these spacers smaller sizes than those allowed by the lithography are obtained. After defining the floating gate region, the method flow goes on with the formation of the interpoly dielectric, which allows the sealing of the POLY1, and of a second polycrystalline silicon layer, called POLY2. The cell is then defined by means of standard etching and photolithography techniques.
However, this method has the drawbacks of a lack of repeatability of the desired size of the spacers in all the areas of the die and on the whole wafer, and of a high faultiness inevitably due to the long sequence of depositions and etchings necessary first to define the above cited sacrificial spacers and then to remove them together with all the other layers different from the polycrystalline silicon layer constituting the floating gate region.
Another known method—which recalls the preceding one—for reducing the spacing size between consecutive floating gate regions exploits the polimerization properties of the etching chemical materials. In accordance with this method, an organic material is deposited below a photosensitive resin, which is exposed with a suitable radiation in the presence of a conventional mask in order to define the floating gate regions. Then the organic material is etched by using a very polimerizing chemistry in order to form a sort of spacer of polymer along the walls of the organic material itself and so, aligning with said spacer, the polycrystalline silicon is subsequently etched, in order to repeatably define a poly-poly spacing of smaller sizes with respect to the lithographic ones. However, this method has several drawbacks linked to its essential polimerizing step. In particular, the polimerization is such as to leave working residues that, especially in case much smaller sizes are realized with than those obtainable by means of lithography, then they can cause short-circuits between adjacent floating gate regions during the definition of the polycrystalline silicon.
The technical problem underlying the present invention is that of devising a method for forming non-volatile memory cells, having such characteristics so as to allow the realization of floating gate regions extremely close with each other, thus overcoming the limitations that still affect the manufacturing methods according to prior art.